Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling

We model the power fluctuation as cycle-to-cycle power gradient and minimize the mean of the power gradients using ILP. We propose scheduling schemes for three modes of datapath design : single supply voltage and single frequency (SVSF), multiple supply voltages and dynamic frequency clocking (MVDFC), and multiple supply voltages and multicycling (MVMC). Various experiments are conducted on selected highlevel synthesis benchmarks. Experimental results in terms of several parameters, such as mean power gradient, mean cycle power, peak power, and power delay product, are presented.